1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device suitable as an input circuit and an output circuit, and particularly relates to a semiconductor device and method of manufacturing the semiconductor device having an improved electrostatic resistance.
2. Background Art
Conventionally, a source diffusion layer and a drain diffusion layer of a transistor constituting an internal circuit of a semiconductor device are formed by a silicide layer in order to reduce the resistance of these layers. Furthermore, since thin film structures have made further advances in recent years, silicide films have been further required not only for the internal circuits but also for transistors constituting the input and output circuits. FIG. 42 shows a plan view of the conventional semiconductor device and FIG. 43 shows a cross sectional view along the Vxe2x80x94V line in FIG. 42. In FIG. 42, the internal wiring is omitted. Here, the semiconductor device shown in FIGS. 42 and 43 is referred to as the first conventional example.
In the first conventional example, a P-well 102 is formed on the semiconductor substrate 101. An element-separating insulating film 103a in the form of a ring is selectively formed on a surface of the P-well 102, and an element-separating insulating film 103b is formed on the boundary layer of the P-well 102 formed on the semiconductor substrate 101.
In an area surrounded by the element-separating insulating film 103a, two N channel MOS transistors 11a and 11b are formed. Three N+ diffusion layers 104a, 104b, and 104c are formed on the surface of the area surrounded by the element-separating insulating film 103a, wherein, the N+ diffusion layer 104a constitutes a source diffusion layer of the MOS transistor 111a, the N+ diffusion layer 104c constitutes a source diffusion layer of the N channel MOS transistor, and the N+ diffusion layer 104b constitutes a drain diffusion layer of the N channel MOS transistors 111a and 111b. That is, the drain diffusion layers of the two N channel MOS transistors 111a and 111b are united.
A P+ diffusion layer 105 is formed on an area sandwiched by two element-separating insulating layers 103a and 103b. Silicide films 106 are formed on the surface of N+ diffusion layers 104a, 104b, 10c, and P+ diffusion layer 105.
Each N channel MOS transistor 111a and 111b comprises a low concentration diffusion layer 107, a gate insulating film 108, a side wall insulating film 109 and a gate electrode 110. The gate electrode 110 is constituted by laminated polycrystalline silicon films and a silicide film.
Furthermore, an interlayer insulating film 112 is formed covering the N channel MOS transistors 111a and 111b. Contact holes reaching each silicide films 106 are formed penetrating the interlayer insulating films 112, and contact plugs 113 are embedded inside those contact holes. Wiring 114 is formed at each contact hole 113.
Since silicide films 106 are formed in conventional semiconductor devices for reduction of the circuit resistance, a problem arises that the conventional input circuits as well as the output circuits are liable to be affected by external electrostatic discharge (ESD), and the electrostatic resistance (resistance to surges) of these circuits decreases.
Japanese Patent (Granted) Publications No. 2773220 and No. 2773221 disclose a semiconductor device in which a region in a portion of the diffusion layer between the source and the drain is left without forming the silicide film. This type of the conventional example is hereinafter referred to as the second conventional example. FIG. 44 is a plan view showing the structure of the second conventional example, and FIG. 45 is the cross-sectional view of along the Wxe2x80x94W line in FIG. 44. Here, the same elements of the second conventional example shown in FIGS. 44 and 45 as those shown of the first convention example shown in FIGS. 43 and 45 are denoted by the same reference numerals and their explanations are omitted.
In the second conventional example, a mask insulating film 118 is formed between the side wall insulating film 109 of each N channel MOS transistor 111a and 111b and the contact plug 113 of the drain in order to partition the N+ diffusion layer 104b into two regions. A silicide layer 106 is formed directly below the mask insulating film 118. Accordingly, the silicide layer 106 formed on the N+ diffusion layer 104b is partitioned into three regions.
In the second conventional example, since the resistance of the drain diffusion layer of each N channel MOS transistor 111a and 111b is higher than that of the first conventional example, the electrostatic resistance of the second embodiment is higher.
In addition, a semiconductor device, in which a high resistance region is formed between the drain diffusion layer of a MOS transistor constituting an output circuit and an output pin, has been disclosed (in U.S. Pat. No. 5,019,888). Hereinafter, this semiconductor device is referred to as called the third conventional example.
In the third conventional example, the high resistance region formed between the drain and the output pin blocks the surge current flowing into the semiconductor device, so that a higher electrostatic resistance that that of the first conventional example is obtained, similar to the second embodiment.
However, although it is possible to improve the electrostatic resistance in the second and third conventional example, a problem arises in the practical semiconductor devices. That is, in practical semiconductor devices, a plurality of transistors are formed in parallel in one well, and stress is concentrated on one transistor and the transistor subjected to the concentrated stress is more likely to be broken.
FIG. 46A is a cross-sectional view showing the propagation path of an surge current in the first conventional example, and FIG. 46B is a diagram showing the change of the voltage applied to the drain diffusion layer due to the surge current. It is noted that the silicide film 106 is omitted.
When an ESD surge current flows into a pad 115 connected to the drain diffusion layer (the N+ diffusion layer 104b), the drain voltage increases, and when the voltage reaches a certain voltage, an avalanche breakdown occurs at a PN junction between the drain diffusion layer (N+ diffusion layer 104b) and the P-well 102. In general, this voltage is called BVDS.
When the ESD surge current further increases, the breakdown current flows to the guard ring (P+ diffusion layer 105) through a parasitic resistor 116 and passes through the ground (GND). Thereby, the voltage of the P-well increases in the proximity of the source diffusion layer (N+ diffusion layer 104a) according to the voltage drop due to the parasitic resistor 116.
When the drain voltage reaches V1 due to the further increase of the ESD surge current, the PN junction between the source diffusion layer ((N+ diffusion layer 104a) and the P-well 102 is forward biased and the parasitic bipolar transistor 117 is turned on, and the N-channel MOS transistor 111a enters snapback. As a result, not only the breakdown current flow from the drain diffusion layer ((N+ diffusion layer 104b) to the guard ring (P+ diffusion layer 105) but also, the snapback current flows from the drain diffusion layer (N+ diffusion layer 104b) to the source diffusion layer ((N+ diffusion layer 104a), and the drain voltage decreases to a certain voltage Vsnp.
Thereafter, if the ESD surge current further increases, the drain voltage increases, and when the drain voltage reaches a certain voltage Vmax, the N-channel MOS transistor 111a is destroyed due to the rise of the temperature.
Since the breakdown current flows through a side end surface portion of the gate of the drain diffusion layer (N+ diffusion layer 104b), the current is small. In contrast, since the snapback current flows from the drain diffusion layer (N+ diffusion layer 104b) to the P well 102, the current becomes relatively large.
Such a snap back phenomenon is similarly generated in the second and third conventional examples having high resistance regions, and the surge current is passed to the ground GND by the same mechanism as in the case of the first conventional example.
However, when the drain diffusion layer is shared by two transistors, two transistors enter snapback simultaneously. Thus, for example, when four transistors are integrated, the transistor breakdown occurs by the following process. FIG. 47A show a schematic structure of a semiconductor device obtained by applying the second conventional example to a structure provided with four transistors, and FIG. 47B is its equivalent circuit. It is noted that the mask insulating film and the silicide film are omitted in FIG. 47A.
Four N channel MOS transistors 121 to 124 are arranged in one P well by disposition of their gate electrodes 121a to 124a in parallel to each other. A drain diffusion layer 126 is shared by two transistors 121 and 122, a source diffusion layer 127 is shared by two transistors 122 and 123, and a drain diffusion layer 128 is shared by two transistors 122 and 124. The drain diffusion layers 126 and 128 are connected to a common pad 130. Around the P well 102, the P+ diffusion layer (the guard ring) is formed, and respective source diffusion layers 125, 127, and 129, and the P+ diffusion layer (the guard ring) 131 are grounded. Resistances are parasitic between respective transistors 121 to 124 and the P+ diffusion layer (the guard ring).
In the semiconductor device constituted described above, although those transistors 122 and 123 simultaneously enters snapback since both transistors 122 and 123 share the source diffusion layer 127. However, the other transistors 121 and 123 do not enter snapback simultaneously, because of the difference in the parasitic resistances. In such a case, since the voltage applied to the drain diffusion layers of the transistors 121 and 124 continues to increase, these transistors 121 and 124 are broken down when the voltage reaches a certain voltage.
It is therefore an object of the present invention to provide a semiconductor device and a method of manufacturing the same, capable of obtaining a high electrostatic resistance.
The semiconductor device of the present invention comprises a resistive element, one end of which is connected to an external terminal; first and second field effect transistors, connected to the other end of the resistive element; wherein, said first and second field effect transistors comprise first and second drain diffusion layers and first and second source diffusion layers, respectively; and the first and second drain diffusion layers are commonly connected directly to the resistive element, and the first and second drain diffusion layers are maintained at an identical voltage.
In the present invention, since the drain diffusion layers of the first and second transistors are at the same potential, even when first transistor enters snapback, the drain voltage of the second transistor changes with that of the first transistor. Accordingly, the stress on the first transistor is relieved and the electrostatic resistance is improved. This effect is obtained for a semiconductor device, in which a resistive element is provided between the external terminal and the drain diffusion layers of two transistors, when the drain diffusion layers of two transistors are commonly connected to the external terminal. Therefore, this effect can be obtained for a semiconductor device without providing a silicide film.
In the present invention, the first and second field effect transistors may respectively comprise first and second silicide films formed on the respective first and second drain diffusion layers.
Moreover, the resistive element is provided between the first and second field effect transistors in the shape of a ring, and the external terminal may be connected to a first diffusion layer which is located inside of the resistive layer and which has the same conductive type as that of the first and second diffusion layers.
Furthermore, the resistive element may be formed by a diffusion layer, whose conductive type is the same as that of the first and second drain diffusion layer. In this case, the resistive element may comprise side wall insulating films of the first and second field effect transistors as well as an insulating film formed on the second diffusion layer.
The resistive element may comprise a second diffusion layer whose conductive type is the same as that of the first and second drain diffusion layer, a dummy gate insulating film formed on the second diffusion layer between the external terminal and the first and second drain diffusion layers, and a dummy electrode, to which a fixed voltage or a voltage of an external terminal is supplied, and which is formed on the dummy gate insulating film
Furthermore, the resistive element may comprise a second diffusion layer whose conductive type is the same as that of said first and second drain diffusion layers, a dummy gate insulating film formed on said second diffusion layer between said external terminal and said first and second diffusion layers, and a dummy electrode in a floating state, which is formed on said dummy gate insulating film.
In addition, the resistive element may comprise second diffusion layer whose conductive type is the same as that of said first and second drain diffusion layers, an element-separating insulating film formed on said second diffusion layer between said external terminal and said first and second drain diffusion layers.
The semiconductor device of the present invention comprises first and second resistive elements, each one end of which is connected to an external terminal; and first and second field effect transistors, each connected to each the other ends of said first and second resistive elements; wherein, each of the first and second field effect transistors comprises first and second drain diffusion layers and first and second source diffusion layers, respectively, and said first and second drain diffusion layers are connected directly to said first and second resistive elements, respectively, and said first and second drain diffusion layers are mutually short circuited.
The semiconductor device of the present invention may comprise one or more than one contact holes formed between the external terminal and the silicide film on the first diffusion layer. In addition, the silicide film on the first diffusion layer is partitioned for each contact hole. The resistive element may be provided for each contact hole.
In the semiconductor device of the present invention, the resistive element and the first and second field effect transistors are preferably provided in one type of circuit portion selected from a group consisting of an input circuit portion, an output circuit portion, and an input/output circuit portion.
The first and second field effect transistors are provided in a first conductive type well and the semiconductor device comprises a second conductive type well, whose side surfaces are surrounded by said first conductive type well and which extends below said resistive element.
Furthermore, the first and second field effect transistors may be one type of transistor selected from a group consisting of a N-channel transistor, a P-channel MOS transistor, and a complementary MOS transistor.
In addition, the semiconductor device comprises an extracting portion provided on at least one of said first and second silicide films for extracting the input signal into the internal circuit.
The method for manufacturing a semiconductor device comprises the steps of: sequentially depositing on a semiconductor substrate a first insulating film for forming a gate insulating film and a polycrystalline silicon film for forming a gate insulating film; patterning said first insulating film and said polycrystalline silicon film for leaving films remaining on at least two portions; forming diffusion layers on said semiconductor substrate using the left film portions composed of the first insulating film and the polycrystalline silicon as the mask; forming a ring-shaped second insulating film on said diffusion layer between the two remaining film portions composed of said first insulating film and said polycrystalline silicon film; and forming silicide films on surfaces of said diffusion layer and said polycrystalline silicon film by use of said second insulating film as the mask.
In addition, in the present invention, the step of sequentially depositing the first insulating film and the polycrystalline silicon film further comprises the step of forming a silicide film on said polycrystalline silicon film.